sn74auch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces476 ? august 2003 1 post office box 655303 ? dallas, texas 75265 member of the texas instruments widebus+ ? family optimized for 1.8-v operation and is 3.6-v i/o tolerant to support mixed-mode signal operation i off supports partial-power-down mode operation sub 1-v operable max t pd of 2.8 ns at 1.8 v low power consumption, 40- a max i cc 8-ma output drive at 1.8 v bus hold on data inputs eliminates the need for external pullup/pulldown resistors latch-up performance exceeds 100 ma per jesd 78, class ii esd protection exceeds jesd 22 ? 2000-v human-body model (a114-a) ? 200-v machine model (a115-a) ? 1000-v charged-device model (c101) description/ordering information this 32-bit edge-triggered d-type flip-flop is operational at 0.8-v to 2.7-v v cc , but is designed specifically for 1.65-v to 1.95-v v cc operation. the sn74auch32374 is particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. it can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. on the positive transition of the clock (clk) input, the q outputs of the flip-flop take on the logic levels set up at the data (d) inputs. a buffered output-enable (oe ) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. oe does not affect internal operations of the latch. old data can be retained or new data can be entered while the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. active bus-hold circuitry holds unused or undriven inputs at a valid logic state. use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. this device is fully specified for partial-power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ordering information t a package ? orderable part number top-side marking ?40 c to 85 c lfbga ? gke tape and reel SN74AUCH32374GKER mk374 ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. copyright ? 2003, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus+ is a trademark of texas instruments. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
sn74auch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces476 ? august 2003 2 post office box 655303 ? dallas, texas 75265 terminal assignments 123456 a 1q2 1q1 1oe 1clk 1d1 1d2 b 1q4 1q3 gnd gnd 1d3 1d4 c 1q6 1q5 v cc v cc 1d5 1d6 d 1q8 1q7 gnd gnd 1d7 1d8 e 2q2 2q1 gnd gnd 2d1 2d2 f 2q4 2q3 v cc v cc 2d3 2d4 g 2q6 2q5 gnd gnd 2d5 2d6 h 2q7 2q8 2oe 2clk 2d8 2d7 j 3q2 3q1 3oe 3clk 3d1 3d2 k 3q4 3q3 gnd gnd 3d3 3d4 l 3q6 3q5 v cc v cc 3d5 3d6 m 3q8 3q7 gnd gnd 3d7 3d8 n 4q2 4q1 gnd gnd 4d1 4d2 p 4q4 4q3 v cc v cc 4d3 4d4 r 4q6 4q5 gnd gnd 4d5 4d6 t 4q7 4q8 4oe 4clk 4d8 4d7 function table (each flip-flop) inputs output oe clk d output q l h h l ll l h or l x q 0 h x x z gke package (top view) j h g f e d c b a 2 134 6 5 p n m l k t r
sn74auch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces476 ? august 2003 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 1oe 1clk 1d1 to seven other channels 1q1 c1 1d a3 a4 a5 a2 2oe 2clk 2d1 to seven other channels 2q1 c1 1d h3 h4 e5 e2 3oe 3clk 3d1 to seven other channels 3q1 c1 1d j3 j4 j5 j2 4oe 4clk 4d1 to seven other channels 4q1 c1 1d t3 t4 n5 n2 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ?0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) ?0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high-impedance or power-off state, v o (see note 1) ?0.5 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o (see note 1) ?0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2) 40 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are obser ved. 2. the package thermal impedance is calculated in accordance with jesd 51-7.
sn74auch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces476 ? august 2003 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) min max unit v cc supply voltage 0.8 2.7 v v high-level input voltage v cc = 0.8 v v cc v v ih high-level input voltage v cc = 1.1 v to 1.95 v 0.65 v cc v ih v cc = 2.3 v to 2.7 v 1.7 v low-level input voltage v cc = 0.8 v 0 v v il low-level input voltage v cc = 1.1 v to 1.95 v 0.35 v cc v il v cc = 2.3 v to 2.7 v 0.7 v i input voltage 0 3.6 v v o output voltage active state 0 v cc v v o output voltage 3-state 0 3.6 v i high-level output current v cc = 0.8 v ?0.7 ma i high-level output current v cc = 1.1 v ?3 ma i oh high-level output current v cc = 1.4 v ?5 ma oh v cc = 1.65 v ?8 v cc = 2.3 v ?9 i low-level output current v cc = 0.8 v 0.7 ma i low-level output current v cc = 1.1 v 3 ma i ol low-level output current v cc = 1.4 v 5 ma ol v cc = 1.65 v 8 v cc = 2.3 v 9 ? t/ ? v input transition rise or fall rate 20 ns/v t a operating free-air temperature ?40 85 c note 3: all unused control inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004.
sn74auch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces476 ? august 2003 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ ? max unit v i oh = ?100 a 0.8 v to 2.7 v v cc ?0.1 v v i oh = ?0.7 ma 0.8 v 0.55 v v oh i oh = ?3 ma 1.1 v 0.8 v v oh i oh = ?5 ma 1.4 v 1 v i oh = ?8 ma 1.65 v 1.2 i oh = ?9 ma 2.3 v 1.8 v i ol = 100 a 0.8 v to 2.7 v 0.2 v v i ol = 0.7 ma 0.8 v 0.25 v v ol i ol = 3 ma 1.1 v 0.3 v v ol i ol = 5 ma 1.4 v 0.4 v i ol = 8 ma 1.65 v 0.45 i ol = 9 ma 2.3 v 0.6 i i all inputs v i = v cc or gnd 0 to 2.7 v 5 a i ? v i = 0.35 v 1.1 v 10 a i bhl ? v i = 0.47 v 1.4 v 15 a i bhl ? v i = 0.57 v 1.65 v 20 a v i = 0.7 v 2.3 v 40 i v i = 0.8 v 1.1 v ?5 a i bhh v i = 0.9 v 1.4 v ?15 a i bhh v i = 1.07 v 1.65 v ?20 a v i = 1.7 v 2.3 v ?40 i ? v = 0 to v 1.3 v 75 a i bhlo ? v i = 0 to v cc 1.6 v 125 a i bhlo ? v i = 0 to v cc 1.95 v 175 a 2.7 v 275 i # v = 0 to v 1.3 v ?75 a i bhho # v i = 0 to v cc 1.6 v ?125 a i bhho # v i = 0 to v cc 1.95 v ?175 a 2.7 v ?275 i off v i or v o = 2.7 v 0 10 a i oz v o = v cc or gnd 2.7 v 10 a i cc v i = v cc or gnd, i o = 0 0.8 v to 2.7 v 40 a c i v i = v cc or gnd 2.5 v 3 pf c o v o = v cc or gnd 2.5 v 5 pf ? all typical values are at t a = 25 c. ? the bus-hold circuit can sink at least the minimum low sustaining current at v il max. i bhl should be measured after lowering v in to gnd and then raising it to v il max. the bus-hold circuit can source at least the minimum high sustaining current at v ih min. i bhh should be measured after raising v in to v cc and then lowering it to v ih min. ? an external driver must source at least i bhlo to switch this node from low to high. # an external driver must sink at least i bhho to switch this node from high to low.
sn74auch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces476 ? august 2003 6 post office box 655303 ? dallas, texas 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) v cc = 0.8 v v cc = 1.2 v 0.1 v v cc = 1.5 v 0.1 v v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v unit typ min max min max min max min max unit f clock clock frequency 85 250 250 250 250 mhz t w pulse duration, clk high or low 5.9 1.9 1.9 1.9 1.9 ns t su setup time, data before clk 1.4 1.2 0.7 0.6 0.6 ns t h hold time, data after clk 0.1 0.4 0.4 0.4 0.4 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see figure 1) parameter from (input) to (output) v cc = 0.8 v v cc = 1.2 v 0.1 v v cc = 1.5 v 0.1 v v cc = 1.8 v 0.15 v v cc = 2.5 v 0.2 v unit parameter (input) (output) typ min max min max min typ max min max unit f max 85 250 250 250 250 mhz t pd clk q 7.3 1 4.5 0.8 2.9 0.7 1.5 2.8 0.7 2.2 ns t en oe q 7 1.2 5.3 0.8 3.6 0.8 1.5 2.9 0.7 2.2 ns t dis oe q 8.2 2 7.1 1 4.8 1.4 2.7 4.5 0.5 2.2 ns operating characteristics, t a = 25 c ? parameter test v cc = 0.8 v v cc = 1.2 v v cc = 1.5 v v cc = 1.8 v v cc = 2.5 v unit parameter test conditions typ typ typ typ typ unit c pd ? (each output) power dissipation capacitance outputs enabled, 1 output switching 1 f data = 5 mhz 1 f clk = 10 mhz 1 f out = 5 mhz oe = gnd c l = 0 pf 24 24 24.1 26.2 31.2 pf c pd (z) power dissipation capacitance outputs disabled, 1 clock and 1 data switching 1 f data = 5 mhz 1 f clk = 10 mhz f out = not switching oe = v cc c l = 0 pf 7.5 7.5 8 9.4 13.2 pf c pd (each clock) power dissipation capacitance outputs disabled, clock only switching 1 f data = 0 mhz 1 f clk = 10 mhz f out = not switching oe = v cc c l = 0 pf 13.8 13.8 14 14.7 17.5 pf ? total device c pd for multiple (n) outputs switching and (y) clocks inputs switching = {n * c pd (each output)} + {y * c pd (each clock)}. ? c pd (each output) is the c pd for each data bit (input and output circuitry) as it operates at 5 mhz (note: the clock is operating at 10 mhz in this test, but its i cc component has been subtracted out). c pd (each clock) is the c pd for the clock circuitry only as it operates at 10 mhz.
sn74auch32374 32-bit edge-triggered d-type flip-flop with 3-state outputs sces476 ? august 2003 7 post office box 655303 ? dallas, texas 75265 parameter measurement information v cc /2 t h t su from output under test c l (see note a) load circuit s1 2 v cc open gnd r l r l data input timing input v cc 0 v v cc 0 v 0 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times inverting and noninverting outputs voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol v cc 0 v input output waveform 1 s1 at 2 v cc (see note b) output waveform 2 s1 at gnd (see note b) v ol v oh t pzl t pzh t plz t phz v cc 0 v v ol + v ? v oh ? v ? 0 v v cc voltage waveforms enable and disable times low- and high-level enabling output output t plh /t phl t plz /t pzl t phz /t pzh open 2 v cc gnd test s1 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , slew rate 1 v/ns . d. the outputs are measured one at a time with one transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. t plh and t phl are the same as t pd . h. all parameters and waveforms are not applicable to all devices. output control v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc v cc /2 v cc /2 0.8 v 1.2 v 0.1 v 1.5 v 0.1 v 1.8 v 0.15 v 2.5 v 0.2 v 2 k ? 2 k ? 2 k ? 1 k ? 500 ? v cc r l 0.1 v 0.1 v 0.1 v 0.15 v 0.15 v v ? c l 15 pf 15 pf 15 pf 30 pf 30 pf figure 1. load circuit and voltage waveforms
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN74AUCH32374GKER active lfbga gke 96 1000 none snpb level-3-220c-168 hr sn74auch32374zker active lfbga zke 96 1000 green (rohs & no sb/br) snagcu level-3-250c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 25-feb-2005 addendum-page 1
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated
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